Implementation and optimization of the motion estimation for H.264 on TI DM6446 DSP

• Main Authors: Chia-Hung Wang, 王佳鴻
• Other Authors: Mon-Chau Shie
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/64826840533284839090

碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === As far as the previous video compression is concerned, H.264 / Advanced Video Coding (AVC) standard provides many efficient methods to improve compression performance. Due to its computational complexity, it is not suitable for real time applications. Motion estimation (ME) is most time consuming process in whole H.264/AVC encoder. ME may consume as high as 80% of the total computational time in H.264/AVC encoder. ME mainly consists of sum of absolute differences (SAD) and sum of absolute transformed differences (SATD) operations in time consumption. So we can optimize SAD and SATD operations in ME to achieve the purpose of real time process. In order to achieve real time process in H.264 encoder, this paper proposes architectures, which are based on SAD operation process and Hadamard Transform process in parallel. The above architectures for reducing the computational time of ME are on TI DM6446 DSP. In the implementation, we adopt the extended instruction set and data-reuse concept on TI DM6446 DSP architecture to accelerate encoding time. The experiment results have shown the optimized SAD and Hadamard Transform operations are able to reduce 90% and 94% of original process time respectively. In whole H.264 encoder, the optimized architectures can save about 40% of total time.