Design of Injection Locked Frequency Dividers and Quadrature Voltage Controlled Oscillator

• Main Authors: Jui-Cheng Han, 韓瑞誠
• Other Authors: Sheng-Lyang Jang
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/10638235703601370712

碩士 === 國立臺灣科技大學 === 電子工程系 === 95 === This thesis presents an injection locked frequency divider (ILFD) employing tunable active inductors for the LC-tanks. The aim of using tunable active inductor is to extend the locking range and scaling down chip size. The CMOS ILFD consists of LC tank voltage-controlled oscillators (VCOs) with cross-coupled switching pair and was fabricated in the 0.18-um 1P6M CMOS technology. The divide-by-2 LC-tank ILFD is performed by adding an injection nMOS between the differential outputs of the divider. Measurement results show that at the supply voltage of 1.8V, the divider free-running frequency is tunable from 1.46 GHz to 2.7 GHz, and at the incident power of -4 dBm the locking range is about 3.4 GHz (79%), from the incident frequency 2.6GHz to 6.0GHz. The core power consumption is 7.2mW and the die area is 0.383*0.379 mm2. A novel low phase noise quadrature voltage controlled oscillator (QVCO) with two coupled Hartley VCOs is proposed and implemented using the standard TSMC 0.18um CMOS 1P6M process. The QVCO employs pMOS as the core to reduce the up-conversion of low-frequency device noise to RF phase noise. It uses super-harmonic coupling technique to couple two differential Hartley VCOs and four small-size coupling transistors to set the directivity of quadrature output phases. At the 1.8V supply voltage, the output phase noise of the QVCO is -125.6dBc/Hz at 1MHz offset frequency from the carrier frequency of 5.06GHz, and the figure of merit is -188.0dBc/Hz. At the supply voltage of 1.8V, the total power consumption is 17.4mW. The die area is 0.982 x0.992 mm2. A novel divide by 2 frequency divider (FD) fabricated in the TSMC 0.35um 2P4M CMOS technology is reported. The FD consists of two single-ended pMOS core Colpitts oscillators coupled with a cross-coupled nMOS pair to generate differential signals. The divide-by-2 LC-tank injection locked frequency divider uses only one injection nMOS with its drain and source connected to the differential outputs of the divider. The measurement results show that at the supply voltage of 3.0V, the divider free-running frequency is tunable from 3.48 GHz to 3.86 GHz, and at the incident power of -3 dBm the locking range is about 0.38 GHz (10.3%), from the incident frequency 6.75GHz to 8.0GHz. The core power consumption is 18mW. The die area is 0.74 x 0.52 mm2. In this thesis we study the operation principle of CMOS divide-by-3 injection locked frequency dividers (ILFDs). The ILFDs can provide differential outputs and are made of an LC-tank resonator with cross-coupled switching pairs, which are stacked in series with two injection MOSFETs. A mathematical formula is proposed to explain qualitatively the circuit operation principle and provide circuit design insights. Under large injection strength, the characteristics of the ILFD show the effect of the 2nd order nonlinearity of input transconductors. A divide-by-3 LC tank ILFD fabricated in the TSMC 0.35um CMOS 2P4M CMOS technology is used to support the design insights of mathematical model.