Development of Digital Signal Processor Based Switched Mode Rectifiers

• Main Authors: Ji-shian Li, 李季憲
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/hjmbus

碩士 === 國立臺灣科技大學 === 電機工程系 === 95 === ABSTRACT This thesis presents the design and implementation of a digital signal processor based switched mode rectifiers for telecommunication power systems. A two-leg parallel-connected circuit with single-phase power factor correction is proposed for ac-dc power conversion. Equal and time-sharing current control is achieved through interleaved pulse-width-modulation to reduce input current ripple. In addition, current-predicted control is used to raise the power factor to unity. On the other hand, dc-dc power conversion is designed with full-bridge power circuit. The zero-voltage switching is accomplished by phase-shifted control to reduce switching loss. The current doubler rectifiers installed at output side can reduce conducting loss of output filtering inductors. Finally, the introduction of load power compensating control in power factor correction circuit will improve system performance and reduce the input current harmonics. In this thesis, switch equivalent circuit is first derived and then simulated by Matlab/Simulink to verify the proposed control strategy. The 32-bit digital signal processor, TMS320F2812, is used to implement the control functions of the system. The control functions of voltage and current closed-loop controls are realized by software to reduce circuit components and improve reliability. In addition, the digital signal processor communicates with personal computer by controller area network interface for real-time monitoring. An experimental system of 48V, 500W output power for 110V, 60Hz input is built with the dc-link voltage of 380V. The efficiency is 89% in full-load operations, and the power factor is 0.993. The total harmonic distortion of input current is 4%, which complies with IEEE Std 519-1992.