Design and Implementation of Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits

• Main Authors: Hsin-Tung Li, 李新通
• Other Authors: 陳建中
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/gyct5d

碩士 === 國立臺北科技大學 === 電子電腦與通訊產業研發碩士專班 === 95 === With the development of electronic technology, the integrated circuits is more and more widely favored, especially in VLSI circuit, embedded system, and analog and digital IC deign. By the maturity of a technology that the integrated circuit at present time, we can integrate different circuits into a single chip, and make the function of our circuit to be more completed, but there are some stray inductances and resistances between circuits and power supply which could product glitches. We call the power bounces and ground bounces [1-2]. If this stray effect is too large, it is possible to make mistake and the result of output may be incorrect. It influence grandly in mixed-signal circuit, so the purpose of this circuit is to reduce power bounce which is produced by stray components. We compare other general LDO, and observe the result. A novel Low Power-Bounce Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits with single Miller compensation capacitor is presented. By utilizing the current mode architecture to suppress power bounce. The proposed Current-to-Voltage-Conversion Dropout Linear Regulator Integrated Circuits have been fabricated in TSMC 0.35μm 2P4M CMOS technology. The measurement results show the settling time which can achieve 400ns with 0.5% error for full load-current. Furthermore, the line and load regulations are 14μV/mA and 4.44ppm/mA, respectively. The dropout current is 1.0741mA for 150mA output current. The measured current efficiency is 99.4168% in 152mA supply current. The active chip area is 226μm x310μm.