Circuit Design for FSK Demodulator of Wireless Communication Applications

• Main Authors: Jun-Yuan Wang, 王俊元
• Other Authors: 邱弘緯
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/rwb3fv

碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 95 === The PLL technique has long been developing in many fields in IC technology. The obvious example is that PLL can apply to duty cycle、pulse-synchronization、frequency synthesizer and clock skew. Therefore, the importance of PLL cannot be ignored. Recently, the main PLL used in many systems is HDPLL; however, there are some difficulties needed to be conquered such as locked-slow and passive component. Low pass filter which composed by resistors and capacitors are to reduce the noise released by output of charge pump. Nevertheless, the exact value of resistor and capacitor in IC is difficult to be controlled and will occupy considerable measures of areas. In this thesis, to avoid wastes the area when operation in low frequency. One measure is to use the ADPLL; besides, the other is to use feedback to save data in the Control Unit. Here it represents an integrator, also regarded as low pass filter, to replace low pass filter of analog. The integrator save large amount of the measures of areas. Area of ADPLL(Include PAD) is 1.107 * 0.97 mm2, frequency is 10MHz, resolution of digital controlled oscillator is 8-bit, oscillator frequency range is from 5.3MHz to 12MHz, and the jitter of LF_ADPLL is 280ps.