Circuit Design for FSK Demodulator of Wireless Communication Applications
碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 95 === The PLL technique has long been developing in many fields in IC technology. The obvious example is that PLL can apply to duty cycle、pulse-synchronization、frequency synthesizer and clock skew. Therefore, the importance of PLL cannot be ignored. Recently, the ma...
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ndltd-TW-095TIT056520162019-06-27T05:10:04Z http://ndltd.ncl.edu.tw/handle/rwb3fv Circuit Design for FSK Demodulator of Wireless Communication Applications 無線通訊應用之頻率鍵移解調變器電路設計 Jun-Yuan Wang 王俊元 碩士 國立臺北科技大學 電腦與通訊研究所 95 The PLL technique has long been developing in many fields in IC technology. The obvious example is that PLL can apply to duty cycle、pulse-synchronization、frequency synthesizer and clock skew. Therefore, the importance of PLL cannot be ignored. Recently, the main PLL used in many systems is HDPLL; however, there are some difficulties needed to be conquered such as locked-slow and passive component. Low pass filter which composed by resistors and capacitors are to reduce the noise released by output of charge pump. Nevertheless, the exact value of resistor and capacitor in IC is difficult to be controlled and will occupy considerable measures of areas. In this thesis, to avoid wastes the area when operation in low frequency. One measure is to use the ADPLL; besides, the other is to use feedback to save data in the Control Unit. Here it represents an integrator, also regarded as low pass filter, to replace low pass filter of analog. The integrator save large amount of the measures of areas. Area of ADPLL(Include PAD) is 1.107 * 0.97 mm2, frequency is 10MHz, resolution of digital controlled oscillator is 8-bit, oscillator frequency range is from 5.3MHz to 12MHz, and the jitter of LF_ADPLL is 280ps. 邱弘緯 2007 學位論文 ; thesis 71 zh-TW |
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碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 95 === The PLL technique has long been developing in many fields in IC technology. The obvious example is that PLL can apply to duty cycle、pulse-synchronization、frequency synthesizer and clock skew. Therefore, the importance of PLL cannot be ignored. Recently, the main PLL used in many systems is HDPLL; however, there are some difficulties needed to be conquered such as locked-slow and passive component. Low pass filter which composed by resistors and capacitors are to reduce the noise released by output of charge pump. Nevertheless, the exact value of resistor and capacitor in IC is difficult to be controlled and will occupy considerable measures of areas.
In this thesis, to avoid wastes the area when operation in low frequency. One measure is to use the ADPLL; besides, the other is to use feedback to save data in the Control Unit. Here it represents an integrator, also regarded as low pass filter, to replace low pass filter of analog. The integrator save large amount of the measures of areas.
Area of ADPLL(Include PAD) is 1.107 * 0.97 mm2, frequency is 10MHz, resolution of digital controlled oscillator is 8-bit, oscillator frequency range is from 5.3MHz to 12MHz, and the jitter of LF_ADPLL is 280ps.
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author2 |
邱弘緯 |
author_facet |
邱弘緯 Jun-Yuan Wang 王俊元 |
author |
Jun-Yuan Wang 王俊元 |
spellingShingle |
Jun-Yuan Wang 王俊元 Circuit Design for FSK Demodulator of Wireless Communication Applications |
author_sort |
Jun-Yuan Wang |
title |
Circuit Design for FSK Demodulator of Wireless Communication Applications |
title_short |
Circuit Design for FSK Demodulator of Wireless Communication Applications |
title_full |
Circuit Design for FSK Demodulator of Wireless Communication Applications |
title_fullStr |
Circuit Design for FSK Demodulator of Wireless Communication Applications |
title_full_unstemmed |
Circuit Design for FSK Demodulator of Wireless Communication Applications |
title_sort |
circuit design for fsk demodulator of wireless communication applications |
publishDate |
2007 |
url |
http://ndltd.ncl.edu.tw/handle/rwb3fv |
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