| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 95 === In recent years, many functions are designed in a chip due to the rapid development of embedded system. Nevertheless, a lot of functions designed in the system will generate many problems, such as larger hardware resources, the worst usage rate of hardware, and more unnecessary power consumption. Dynamic reconfiguration can improve numerous aforesaid questions because it has the software-like property which can change hardware module when the system is executing. Many researches of the dynamic reconfigurable system realized with single module region recently. Most of researchers describe the work of multi-region reconfigurable system by proposed methodology in comparison with the single region of reconfigurable system architecture. They used simulation result to determine the quality of proposed reconfigurable system, but did not realize the architecture in hardware platform. In this thesis, we design and implement a new multi-region architecture for reconfiguration system which consists of the wrapper, bus macro, and arbiter. The wrapper and bus macro can connect with various kinds of hardware module and transmit multi-data. The arbiter manages the data flow between hardware module and MicroBlaze, and decides the region which will be reconfigured. Because these functions are implemented, the system just needs to process the action of information input and output for our architecture. The system need not know which region the information will be executed. Experimental results show that our proposed architecture can support multi-module, direct detecting hardware module function of arbiter, 160 I/O ports of wrapper, and multi-data of bus macro.
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