A Novel Two-Layer Routing Algorithm for Cell-Based Design Circuits under Grid Routing Model

• Main Authors: Chia-Jung Liu, 劉家榮
• Other Authors: Jiann-Chyi Rau
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/27759308903128608412

碩士 === 淡江大學 === 電機工程學系碩士班 === 95 === In recent year the advance of semiconductor manufacturing technology has led to a great development, the routing problems of digital circuit design become more and more complex. The following problems that are the circuit whether it can achieve 100% routing or not and the need of total routing area…etc. If the circuit has the segments that can be route, the router will spend much more time on re-route. Therefore, after placed the components we begin analyzing the routing data and other related data that are need for routing. Using standard cell style to design digital circuits, the first we will map the designed circuit in standard cell library and we will place the components preliminary then route the nets. In this paper, we use the grid based routing model to deal with the routing problems. The advantage of using grid based routing model is the model can reduce the complexity of routing. If the router routing the circuit base on this routing model, it will not violate the design rules check (DRC) and it will reduce more the design time and design difficulty. Following, we will base on the grid routing model to deal with the unrouted problems that maybe occur during routing the nets. We propose a novel approach to solve the unrouted problems. After we placed the components of circuit, we will get some related data that are need for routing and we will find the unrouted conditions from these data beforehand. After that using our propose algorithm to solve the unrouted circuits in advance and using our approach can achieve 100% routing results and it can finish in linear time. Complete all of the nets routing, we can add some space selectively to reduce the numbers of channel tracks. Optimize the numbers of channel tracks that is helpful to reduce the channel height. Finally, we use the ISCAS’85 benchmarks to simulate the results. The ISCAS’85 benchmarks are a group of combinatorial logic circuits that we know how many components、inputs and outputs of circuits. In the simulation results, the area overhead only increase 6.34% in average to solve all of the unrouted segments and it can guarantee to achieve 100% routing.