All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture

碩士 === 元智大學 === 通訊工程學系 === 95 === With modulo-N arithmetic and a set of reference square waveforms, a new architecture of high-performance digital frequency synthesizer is devised, where the reference square waveforms with the same frequency but different phases are passed through a multiplexer to o...

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Bibliographic Details
Main Authors:	Hsi-Kuei Liu, 劉喜貴
Other Authors:	Yaw-Geng Chau
Format:	Others
Language:	zh-TW
Published:	2007
Online Access:	http://ndltd.ncl.edu.tw/handle/74683014954700645672

id	ndltd-TW-095YZU05650026
record_format	oai_dc
spelling	ndltd-TW-095YZU056500262016-05-23T04:17:53Z http://ndltd.ncl.edu.tw/handle/74683014954700645672 All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture 以Modulo-N演算與Flying-Adder為基礎之全數位頻率合成器 Hsi-Kuei Liu 劉喜貴碩士元智大學通訊工程學系 95 With modulo-N arithmetic and a set of reference square waveforms, a new architecture of high-performance digital frequency synthesizer is devised, where the reference square waveforms with the same frequency but different phases are passed through a multiplexer to obtain the maximal frequency with an incrementer. A Gray encoder is designed to eliminate the glitch problem. Pre- and post-layout simulation results based on the TSMC 0.18um cell-based implementation are illustrated to validate the design, which can be used for TSMC 0.18 um realization. Yaw-Geng Chau 趙燿庚 2007 學位論文 ; thesis 50 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 元智大學 === 通訊工程學系 === 95 === With modulo-N arithmetic and a set of reference square waveforms, a new architecture of high-performance digital frequency synthesizer is devised, where the reference square waveforms with the same frequency but different phases are passed through a multiplexer to obtain the maximal frequency with an incrementer. A Gray encoder is designed to eliminate the glitch problem. Pre- and post-layout simulation results based on the TSMC 0.18um cell-based implementation are illustrated to validate the design, which can be used for TSMC 0.18 um realization.
author2	Yaw-Geng Chau
author_facet	Yaw-Geng Chau Hsi-Kuei Liu 劉喜貴
author	Hsi-Kuei Liu 劉喜貴
spellingShingle	Hsi-Kuei Liu 劉喜貴 All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
author_sort	Hsi-Kuei Liu
title	All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
title_short	All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
title_full	All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
title_fullStr	All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
title_full_unstemmed	All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture
title_sort	all digital frequency synthesizer based on modulo-n algorithm and flying-adder architecture
publishDate	2007
url	http://ndltd.ncl.edu.tw/handle/74683014954700645672
work_keys_str_mv	AT hsikueiliu alldigitalfrequencysynthesizerbasedonmodulonalgorithmandflyingadderarchitecture AT liúxǐguì alldigitalfrequencysynthesizerbasedonmodulonalgorithmandflyingadderarchitecture AT hsikueiliu yǐmodulonyǎnsuànyǔflyingadderwèijīchǔzhīquánshùwèipínlǜhéchéngqì AT liúxǐguì yǐmodulonyǎnsuànyǔflyingadderwèijīchǔzhīquánshùwèipínlǜhéchéngqì
_version_	1718278960039591936

All Digital Frequency Synthesizer Based on Modulo-N Algorithm and Flying-Adder Architecture

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