Design of a 1-V 10-Bit Successive Approximation Analog-to-Digital Converter

• Main Authors: Jing-Mao Lin, 林經貿
• Other Authors: Tsung-Heng Tsai
• Format: Others
• Language: zh-TW
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/14200763484023935656

碩士 === 國立中正大學 === 電機工程所 === 96 === Following the process evolution, the technologies go into deep sub-micron eras. The supply voltage has to be scaled down and the demand for circuits under battery operated is increased, such as portable equipments, sensor devices, bio-medical applications. This thesis presented a 1v, 10bit successive approximation ADC(SA-ADC). In order to increase the resolution of the SA-ADC, the bootstrap technique is used on the sample and hold circuit. A pre-amplifier is used in the comparator circuit. The chip is implemented in TSMC 0.18μm 1P6M CMOS technology. Measurement results show that the SNDR and ENOB of the SA-ADC with an input frequency of 501kHz under sampling frequency of 1.04MHz are 47.29dB and 7.56bit, respectively. The DNL is about +1.22/-1.0 LSB, and INL is about +2.66/-2.44 LSB. The total power consumption is 86μW.