Study on Partition-Based Routing Problems in Electronic Design Automation

• Main Authors: Hsin-Hsiung Huang, 黃信雄
• Other Authors: Tsai-Ming Hsieh
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/56426655745346347778

博士 === 中原大學 === 電子工程研究所 === 96 === In this thesis, we study how to improve the routing results in the electronic design automation, EDA, by using the partition-based method. We observe the maximum source-to-terminal delay can be improved by the partition-based method, which takes the source position to divide the routing area into k sub-regions and individually constructs each routing tree for each sub-region. In the thesis, we will discuss the partition-based routing by listing the problems and giving the effective solutions. First, we study two Manhattan-architecture routing problems and propose two effective algorithms to solve them. For the first problem, we propose a timing-driven routing tree construction, which utilizes the partitioning to minimize the maximum source-to-terminal delay and adds the terminal-to-terminal edges in the spanning graph to minimize the total wirelength, makes a balance between the delay and wirelength. For the second problem, we propose a hybrid approach, which analyzes the density distribution by two density functions and partitions the routing area into a set of sub-regions, simultaneously minimizes the total wirelength and runtime. In contrast to the traditional method, our algorithm is more flexible to automatically apply the multiple approaches for each sub-region by two density functions. Second, we study two X-architecture routing problems and provide two effective algorithms to solve them. For the first problem, a partition-based method, which partitions the routing area into a set of sub-regions and applies the delaunay triangulation algorithm for each sub-region, is to minimize the maximum source-to-terminal delay and the total wirelength. For the second problem, we incorporate two novel concepts, including the virtual obstacles for handling the nonrectangular obstacles and the virtual nodes to minimize the total wirelength. Furthermore, we partition the routing area and apply the above new approach to construct the routing tree with rectangular/nonrectangular obstacles for each sub-region. In contrast to the previous works, our approach can handle the timing-driven routing with the obstacles.