Functiional Self High-Precision Speed-Binning Mechanism for IP Cores with Multi-Voltage and Multi-Clock in SoC Chip

• Main Authors: Ming-Chien Tsai, 蔡明倩
• Other Authors: Ching-Hwa Cheng
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/09637823135724971833

碩士 === 逢甲大學 === 電子工程所 === 96 === VLSI’s process and design technology advances have been developed to have high speed and System-on-a-Chip (SoC). However, the complexity of circuit design has increased, and the circuit testing has new challenges. It is very difficult to control and test internal circuit from the input and output of SoC. We consider that the external ATE (Automation Test Equipment) has high cost, high test complexity, and inaccuracy. Therefore, this thesis uses wireless-testing platform to solve ATE’s traditional drawback. We achieve testing the chip by wireless-testing mechanism. This method decreases ATE’s cost, and it will become the main SoC testing technique in the future. It is different for traditional at-speed testing, this thesis apply Functional Delay Testing technique to supply test patterns by slower frequency. We designed a clock edge tuning circuit to measure the delay fault in CUT (Circuit Under Test). Our target is realizing at-speed testing IP cores with multi-voltage and multi-frequency. The thesis presents the dynamic TSPC (True Single Phase Clocking) technique for the interface of data transmission in multi-voltage and multi-frequency IP cores. This method also solves data transmission problems in multi-voltage. Our interface adopts a handshaking mechanism, guaranteeing that there is no data loss when communication is done between two different clock domains.