Design of a Loss-of-Signal Detector in Limiting Amplifiers
碩士 === 明新科技大學 === 電子工程研究所 === 96 === The paper have designed the Loss of signal (LOS) Detector circuit which applies Limiting amplifier in the optical communication field. The device is used the TSMC 0.35μm technology for simulated and designed. The LOS circuit is implemented by three part which is...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88366011957710121442 |
| Summary: | 碩士 === 明新科技大學 === 電子工程研究所 === 96 === The paper have designed the Loss of signal (LOS) Detector circuit which applies Limiting amplifier in the optical communication field. The device is used the TSMC 0.35μm technology for simulated and designed. The LOS circuit is implemented by three part which is Root Means Square (RMS), Comparator and Output Buffer.
The First stage of LOS is a root mean square detector (RMS) which is implemented by rectifier and low pass filter. The circuit which transforms a AC signal to DC signal is based on one differential amplifier and a rectifier filter. The output signal is changed by amplitude of input signal.
The second-stage is a comparator which has Emitter-Coupled Pair With Active Load. The structure of the circuit always uses in the Analog to Digital Circuit (ADC). The circuit has hysteresis effect. Comparator which output a binary signal compares two different analog signals to be input signal. In this circuit, one of the input port is connected by one reference voltage.
The third-stage is a output buffer which is designed by Schottky- TTL (STTL). The circuit which uses a passive pull-up circuit to do a output circuit transforms the input voltage to the base gate of current. The circuit which is like as traditional Transistor Transform Logic (TTL) circuit uses the cramp effect of Schottky transistor to do as unsaturation switch, but the charge doesn’t have the time delay.
The paper analyses and simulates the device using H-Spice which is a simulated software for electronic circuit. The supply power is 5 voltage. The input signal is simulated by Limiting amplifier. Total loss power is about 110mW with 3dB hysteresis. The layout is passed and simulated DRC and LVS in Cadence.
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