Wideband PLL-Based Frequency Synthesizers
碩士 === 國立中興大學 === 電機工程學系所 === 96 === In this thesis, the main purpose is to design the wideband Phase-Lock Loop (PLL), and to realize a fractional-N frequency synthesizer providing the LO signal for Digital Television (DTV) ATSC standard. In the wideband PLL system, the damping factor (ξ) and natura...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96133508346684883836 |