System-Level Bus-Based Communication Architecture Exploration for Power and Performance Using Modified Simulated Annealing Algorithm

• Main Authors: Chih-Hsien Lee, 李致賢
• Other Authors: Lih-Yih Chiou
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/27943636962965490473

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === Upon entering System-on-Chip (SoC) era, more and more Intellectual Properties (IPs) are integrated into the same chip. IPs communicate through communication architectures. The communication architectures consume lots of performance and power, so how to select suitable communication architectures is an important problem. However, the enormous exploration spaces impose challenges for exploration. Now, a speedy and effective communication architecture exploration approach is proposed in this work. This approach not only considers performance of the system but also power. Furthermore, it can provide the power/performance trade-off on different communication architectures, which helps designers to determine system architectures for different applications. In the case studies, we demonstrate how effective and speedy this approach is. This approach can reduce the exploration space to speed up the exploration time. In the future, we can annotate some power models in this work and get a very powerful and precise communication architecture exploration approach.