System-Level Bus-Based Communication Architecture Exploration for Power and Performance Using Modified Simulated Annealing Algorithm
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === Upon entering System-on-Chip (SoC) era, more and more Intellectual Properties (IPs) are integrated into the same chip. IPs communicate through communication architectures. The communication architectures consume lots of performance and power, so how to select...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/27943636962965490473 |