Design of CMOS RFICs for MB-OFDM UWB RF Receiver

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 96 === This thesis presents the design on CMOS RFICs for MB-OFDM UWB RF Receiver. The RFICs are designed with TSMC 0.18 µm 1P6M standard CMOS fabrication process supplied. The first part presents 3-5-GHz low voltage broadband down-conversion and up-conversion mixers,...

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Bibliographic Details
Main Authors: Kuo-feng Wei, 魏國峰
Other Authors: Huey-ru Chuang
Format: Others
Language:zh-TW
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/94282377238321242338
Description
Summary:碩士 === 國立成功大學 === 電腦與通信工程研究所 === 96 === This thesis presents the design on CMOS RFICs for MB-OFDM UWB RF Receiver. The RFICs are designed with TSMC 0.18 µm 1P6M standard CMOS fabrication process supplied. The first part presents 3-5-GHz low voltage broadband down-conversion and up-conversion mixers, the second part is 3-5-GHz broadband receiver front-end., and the third part is 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system. The 3-5-GHz low voltage broadband CMOS down-conversion mixer employs a folded switched transconductor topology. Measured results are: a maximum conversion gain of 10-13 dB, minimum noise figure of 7.5-8.3 dB, maximum IIP3 of -7.5- -5 dBm, LO-RF isolation of about 50 dB, and a dc power only consumption of 2.5 mW at 1.2 V power supply. The 3-5-GHz low voltage broadband CMOS up-conversion mixer employs a folded switched topology. The mixer consists of a voltage-to-current (V-I) converter and a folded Gilbert switching quad. Measured results are: a maximum conversions gain of 5.3 dB, maximum OIP3 of -0.3 dBm, LO-IF isolation of about 37 dB, and a dc power only consumption of 2.7 mW at 1.2 V power supply. The 3-5-GHz RF receiver front-end includes a LNA with a cascade topology and a I/Q mixer employing a single-balanced Gilbert cell topology. A pMOS current source is used to set transconductor and switching stage current independently. The quadrature LO signal generated by quadrature poly phase filter. Measured results are: a maximum conversion gain of 18-27 dB, minimum noise figure of 6-9.2 dB, maximum IIP3 of -11- -5.5 dBm, LO-RF isolation of about 51 dB, and a dc power only consumption of 47.1 mW at 1.8 V power supply. The 3-5-GHz CMOS RF receiver integrated with frequency synthesizer for UWB MB-OFDM system includes a LNA, a single-balanced Gilbert cell mixer and a MB-OFDM UWB CMOS mode-1 frequency synthesizer. Measured results are: a maximum conversion gain of 17-24.1 dB, minimum noise figure of 5.8-22.4 dB, maximum IIP3 of -18- -12 dBm, RF-IF isolation of about 30 dB, and a dc power only consumption of 88.2 mW at 1.8 V power supply.