| Summary: | 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 96 === In this thesis, we design an out-of-order superscalar microprocessor which is based on the popular ARM microprocessor. Many micro-architecture complexities arise when transforming an ARM-based pipelined processor into a superscalar one. The first is to choose a superscalar architecture from a reservation station based model or a register update unit based processor model. And the second one is to deal with the special characteristics of the ARM architecture which has multiple execution modes, multi-banked register files, addressing modes, CICS-like instructions, and conditional executing instructions.
Based on the simulation results, we use the register update unit architecture to design a nine-stage pipelined superscalar processor. We develop techniques to handle the CICS-like instructions and conditional executing instructions for the ARM ISA, and find that the operations of conditional executing instructions are the key factor that affects the performance. The proposed superscalar processor has achieved 30% higher performance than that of the traditional five-stage pipeline processor.
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