QDIP Readout Circuit with Modified Regulated Cascode Circuit and In-pixel Integration

• Main Authors: Yao-Bing Yang, 楊耀賓
• Other Authors: Meng-Lieh Sheu
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/59447850194640170520

碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === Quantum dot infrared photodetector (QDIP) focal-plane-array (FPA) imaging systems have a wide range of military, medical, industrial, and scientific applications. Accompany with the progress of semiconductor fabrication, micromachining and material technologies, the performance of infrared detectors and the integration of detector with readout circuit have much increased their applications. In this thesis, we will present a readout circuit for quantum dot infrared photodetector focal-plane-array imaging system. The readout circuit employs a modified regulated cascode to stabilize bias of QDIP. In-pixel dark current cancellation, sensed current integration and in-pixel switched integration capacitor are also employed in the readout circuit. Adopting the mentioned techniques of readout circuit, two chips with 8x8 array readout circuit are implemented by using TSMC 0.35μm Mixed-Signal 2P4M CMOS process provided by Chip Implementation Center. The chips work at 5V power supply and operate at 1MHz clock rate. The measurement results show that the two fabricated chips can generate an output range of 2V and 4V, respectively, when sensing current from 0nA to 100nA. The power consumption of the chip is less than 3.3mW.