| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === This thesis aim is to design ultra wideband low noise amplifiers, 24-GHz and 53-GHz CMOS low noise amplifiers. Study the theme can be divided into three parts：
In first part, 3.1 ~ 10.6 GHz low noise amplifier is designed for ultra wideband (UWB). The mainly three types of low noise amplifier were using current-sharing technique to achieve low-power consumption. In order to achieve not only high but also flat gain and small group-delay-variation at the same time, the series and shunt inductive peaking were adopted in the output stage to enhance the frequency of the dominant pole and then expand 3-dB bandwidth of the LNA. In the part of input stage, the R-C negative feedback can achieve impedance matching and reduce chip area.
First, we design two types of LNA in standard 0.18 um CMOS technology and use the difference gate inductor of series inductive peaking at the same time. The measured results of the first type LNA (lower gate inductor) show the maximum S21 of 13.5 dB, S11 below -12 dB, S22 below -11.8 dB and flat noise figure of 3.61~ 4.68 dB form 3.1 to 10.6 GHz. The measured results of the second type LNA (larger gate inductor) show the flatter S21 of 12.24±0.62 dB. The S11 and S22 below -8.5 dB and flat noise figure of 3.74 ~ 4.74 dB over 3.1-10.6 GHz while consuming 10.33 mW. In order to pursue better performances of the LNA, the third type of LNA is implemented in standard 0.13 um CMOS technology. The measured results show that the 3-dB bandwidth is 13 GHz, the power gain (S21) of 7.92±0.23 dB, input return loss (S11) and output return loss (S22) below -14 dB, and the group-delay-variation only ±16.7 ps over 3.1-10.6 GHz, minimum noise figure of 2.5 dB is achieved at 10.5 GHz while consuming 10.68 mW. The results show that the LNA is suitable for UWB pulse-radio system applications.
In the second part, 21~27 GHz low noise amplifier is implemented in standard TSMC 0.18 um CMOS technology and suitable for radar system. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages and a cascode amplifier. The current-sharing technique with inductive peaking is adopted for bandwidth enhancement in the second and third stage. The measured results show that the 3dB bandwidth is 8.5 GHz, the S21 of 9.3±1.3 dB, S11 and S22 below -8.2 dB, noise figure of 4.9~6.1 dB, and the very small group-delay-variation (±8.1 ps) over 21-27 GHz while consuming 27 mW.
The last part, low-power-consumption 53-GHz (V-band) low-noise amplifier (LNA) using standard 0.13 um CMOS technology is reported. To achieve sufficient gain, this LNA is composed of four cascaded common-source stages. Current-sharing technique is adopted in the third and the fourth stage to reduce the power dissipation. The output of each stage is loaded with a LC parallel resonance circuit to maximize the gain at the design frequency. This LNA achieved voltage gain (AV) of 14 dB with very low noise figure (NF) of 6.13 dB, and input referred 1-dB compression point (P1dB-in) of –20 dBm at 53 GHz. It consumed very small dc power of 10.56 mW.
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