Reconfigurable Backpropagation Neural Network Implementation for FPGA
碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we proposed reconfigurable back propagation neural network (BPNN) hardware architecture. This architecture makes BPNN has more flexibility. It can process many complex applications and avoid synthesis again. User writes instructions into the Prog...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/44687836984947728873 |
| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we proposed reconfigurable back propagation neural network (BPNN) hardware architecture. This architecture makes BPNN has more flexibility. It can process many complex applications and avoid synthesis again. User writes instructions into the Program Memory (PM) to reconfigure neural network architecture. The single neuron computation architecture executes reconfigurable BPNN hardware architecture. This computation architecture achieves resource sharing and reduces area in hardware. We proposed new reconfigurable feed-forward neural network hardware architecture. The purpose of new architecture reduces number of hidden layers in multilayer feed-forward neural network. The computation architecture is the same as BPNN hardware architecture. Finally, it uses Xilinx – ISE to synthesis BPNN and verification. This architecture verification and comparison are in the field-programmable gate arrays (FPGAs).
|
|---|