Design of PLL-Based Frequency Synthesizer for DSP in MP3 Player

• Main Authors: Kao Ming Cheng, 高明正
• Other Authors: Kuei-Ann Wen
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/21868013160222381300

碩士 === 國立交通大學 === 電機學院碩士在職專班電子與光電組 === 96 === MP3 compression format has been widely used in multimedia player and storage application for its convenient. It is an essential standard for digital audio compression nowadays. A MP3 player can implement different sampling rate in software or hardware design method. It is usually implemented in hardware design method especially for hand-held devices. It can be realized by adjusting the operating frequency of digital signal processing circuit. In addition, it will reduce the power consumption since the power consumption of digital circuit is proportional to operating frequency. In this thesis, the design of PLL-based frequency synthesizer for a digital signal processor (DSP) is described. It provides a programmable clock signal with variable frequency for DSP to operate in different condition. For higher speed and performance, a clock signal with higher frequency is used. For power saving requirement, a lower frequency clock signal is used. This circuit was fully integrated with a 0.18 μm 1P6M CMOS process. An 24 MHz crystal oscillator is used as a fundamental clock for this PLL. To generate the reference frequency for this PLL, a frequency divider is used to divide down the 24 MHz clock first. In addition, there includes a programmable frequency divider for frequency synthesizer. The frequency synthesizer is designed to generate a clock frequency from 31.059 MHz to 81.882 MHz. The supply voltage is 1.8 V with a ± 10% tolerance. The PLL has been tested and it can lock to all frequency range. The measured jitter is 85ps at 81.882 MHz, and the maximum current consumption is around 570uA.