Experiments of Taguchi’s orthogonal arrays for on-chip ESD protection design in integrated circuits

• Main Author: 張琨暐
• Other Authors: 陳科宏
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/46346903312962890172

碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 96 === This thesis proposes a Taguchi’s orthogonal arrays concept of which the Electrostatic Discharge (ESD) protection quality can be effectively improved by using a simple orthogonal array experimental design as well as a simplified factor response analysis and referring to small quantity of experimental statistics for further analysis. In other words, using few experimental combinations can lead to the acquisition of useful information. As we know, the state of the art manufacture technology of integrated circuits leads to considerable device scale-down. However, the Electrostatic Discharge damage does not fade out while the device size is shrinking. On the other hand, the smaller IC size is, the lower ESD robustness it has. To avoid ESD damage, many of solutions to ESD protection have been proposed. One of the thorniest problems research face is testing factor complex and efficiency decline in the present day. The ESD protection chip with a lot of pins and layout area affects the testing time and cost. It’s an important issue for designer to understand ESD phenomena in increase robust quality design, decrease testing time and cost. Thus, the importance of this thesis is the introduction of the Taguchi’s orthogonal arrays concept on ESD.