| Summary: | 博士 === 國立交通大學 === 電子工程系所 === 96 === In this thesis, we utilize cerium oxide nanoparticle as a charge-trapping layer to fabricate nonvolatile memory. The cerium oxide nanocrystals formed self-assembled under different rapid-thermal annealing (RTA) ambient. This high-k nanocrystals layer replaces the silicon nitride layer in the SONOS-type memory structure. Different program/erase (P/E) methods are also proposed low power applications. This nanocrystals nonvolatile memory device will have good properties in terms of considerably large memory window, higher P/E speed, long data retention, and good endurance.
First, we present a nonvolatile SONOS-type flash memory that using cerium oxide (CeO2) nanocrystals as the trapping storage layer. These CeO2 nanocrystal memories exhibit long data retention, and good reliability, even for the cells subjected to 10k P/E cycles. These features suggest that such cells are very useful for high-density two-bit nonvolatile flash memory applications.
Then, we demonstrate the effects of the post-deposition different annealing ambient for the CeO2 trapping layer on the performance of SONOS-type flash memories. It was found that the CeO2 nanocrystals memory with different retention time caused by annealing ambient influence the deep-trapping level. However, the basic electrical operation characteristics are similar. This was ascribed to the larger amount and the shallower energy levels of the crystallization-induced traps. Finally, in the aspect of disturbances, we show only insignificant disturbances properties presented in the normal operation.
Next, we utilized the stack tunneling layer to replace conventional SiO2 tunneling layer. A nonvolatile SONOS-type flash memory device also used CeO2 nanocrystals as a charge trapping layer. It was demonstrated that the fabricated memories exhibit higher program/erase speed and long retention time. In particular, two-bit per cell operation has been successfully demonstrated.
Finally, we study nonvolatile CeO2 nanocrystal memory with no body contact (substrate floating). The operating voltage can reduce 1 V at program mode. Nevertheless, the date retention is similar. We also measure charge-pumping current for different programming methods to observe the SONOS-type memory border traps.
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