A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric
碩士 === 國立交通大學 === 電子工程系所 === 96 === Metal-gate/high-κ is required for 45 node CMOS technology to reduce the intolerable leakage current of the conventional SiO2-based CMOSFETs. The desirable effective work function of metal gate should be close to conduction band edge of Si (~4 eV) for nMOSFETs. How...
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ndltd-TW-096NCTU54281072015-10-13T13:51:49Z http://ndltd.ncl.edu.tw/handle/67014896546812269266 A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric 使用完全矽化閘極-高介電常數介電質之低臨界電壓金氧半電晶體 Guan Lin Chen 陳冠霖 碩士 國立交通大學 電子工程系所 96 Metal-gate/high-κ is required for 45 node CMOS technology to reduce the intolerable leakage current of the conventional SiO2-based CMOSFETs. The desirable effective work function of metal gate should be close to conduction band edge of Si (~4 eV) for nMOSFETs. However, one of the key challenges for metal-gate/high-κ is the large threshold voltage due to Fermi-level pinning effect. In order to reduce the threshold voltage, it is one of the solutions to use the fully silicided gate. In this thesis, we have fabricated n-MOSFETs using fully sicilided (FUSI) HfSix gate and Hf0.7La0.3ON gate dielectrics. From the measurement, a low threshold voltage of 0.18 V and a peak electron mobility of 215 cm2/V-s is obtained at 1.2 nm equivalent oxide thickness (EOT). Also, the leakage current is about 5 orders of magnitude lower than that of SiO2 at the same EOT. In addition, the gate-first process and thermal stability of HfSix/Hf0.7La0.3ON nMOSFETs make them compatible with current VLSI fabrication process. Albert Chin 荊鳳德 2008 學位論文 ; thesis 56 en_US |
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碩士 === 國立交通大學 === 電子工程系所 === 96 === Metal-gate/high-κ is required for 45 node CMOS technology to reduce the intolerable leakage current of the conventional SiO2-based CMOSFETs. The desirable effective work function of metal gate should be close to conduction band edge of Si (~4 eV) for nMOSFETs. However, one of the key challenges for metal-gate/high-κ is the large threshold voltage due to Fermi-level pinning effect. In order to reduce the threshold voltage, it is one of the solutions to use the fully silicided gate.
In this thesis, we have fabricated n-MOSFETs using fully sicilided (FUSI) HfSix gate and Hf0.7La0.3ON gate dielectrics. From the measurement, a low threshold voltage of 0.18 V and a peak electron mobility of 215 cm2/V-s is obtained at 1.2 nm equivalent oxide thickness (EOT). Also, the leakage current is about 5 orders of magnitude lower than that of SiO2 at the same EOT. In addition, the gate-first process and thermal stability of HfSix/Hf0.7La0.3ON nMOSFETs make them compatible with current VLSI fabrication process.
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Albert Chin |
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Albert Chin Guan Lin Chen 陳冠霖 |
author |
Guan Lin Chen 陳冠霖 |
spellingShingle |
Guan Lin Chen 陳冠霖 A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
author_sort |
Guan Lin Chen |
title |
A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
title_short |
A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
title_full |
A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
title_fullStr |
A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
title_full_unstemmed |
A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric |
title_sort |
low threshold voltage n-mosfet using fully silicided gate and high-κ dielectric |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/67014896546812269266 |
work_keys_str_mv |
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