A Low Threshold Voltage n-MOSFET Using Fully Silicided Gate and High-κ Dielectric

• Main Authors: Guan Lin Chen, 陳冠霖
• Other Authors: Albert Chin
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/67014896546812269266

碩士 === 國立交通大學 === 電子工程系所 === 96 === Metal-gate/high-κ is required for 45 node CMOS technology to reduce the intolerable leakage current of the conventional SiO2-based CMOSFETs. The desirable effective work function of metal gate should be close to conduction band edge of Si (~4 eV) for nMOSFETs. However, one of the key challenges for metal-gate/high-κ is the large threshold voltage due to Fermi-level pinning effect. In order to reduce the threshold voltage, it is one of the solutions to use the fully silicided gate. In this thesis, we have fabricated n-MOSFETs using fully sicilided (FUSI) HfSix gate and Hf0.7La0.3ON gate dielectrics. From the measurement, a low threshold voltage of 0.18 V and a peak electron mobility of 215 cm2/V-s is obtained at 1.2 nm equivalent oxide thickness (EOT). Also, the leakage current is about 5 orders of magnitude lower than that of SiO2 at the same EOT. In addition, the gate-first process and thermal stability of HfSix/Hf0.7La0.3ON nMOSFETs make them compatible with current VLSI fabrication process.