| Summary: | 碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === FFT module is an indispensable part for wireless and mobile communication, especially when broadband wireless systems require a high speed and low power hardware module for its packet-based high-speed data transfer. This has made the design of FFT processor a critical requirement for the next generation wireless systems. In general, FFT module is designed for specific system. Therefore, it is desirable to design an adaptive FFT module for different standards. This thesis adopts processor flexible characteristic and ASIC accelerated mechanism to set up a flexible FFT module which can meet IEEE 802.11n/16e standards. Besides, we propose optimized time schedule in the SISO/MIMO systems. After processor computational analysis, 64-point branch FFT of ASIC can be applied in proposed system and it computes 16-bit input data at the 85 MHz throughput rate. After that, we compare various pipeline-based FFT architectures of ASIC and analyze their characteristic. Finally, it not only verifies the 64-point branch FFT on FPFA, but also checks proposed time schedule which can satisfy IEEE 802.11n/16e specification.
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