Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication

博士 === 國立彰化師範大學 === 電機工程學系 === 96 === In the recent years, the low-power, low-cost, and high integration have become the trend for communication ICs. In this thesis, we proposed a low-power low noise amplifier (LNA) for UWB receiver, a low-power mixer for IEEE 802.11a receiver and a low-power mixer...

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Main Authors: Jun-da chen, 陳俊達
Other Authors: Zhi-Ming Lin
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/25221535897800912744
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spelling ndltd-TW-096NCUE54420042016-05-18T04:12:56Z http://ndltd.ncl.edu.tw/handle/25221535897800912744 Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication 低電壓無線通訊CMOS射頻晶片研製 Jun-da chen 陳俊達 博士 國立彰化師範大學 電機工程學系 96 In the recent years, the low-power, low-cost, and high integration have become the trend for communication ICs. In this thesis, we proposed a low-power low noise amplifier (LNA) for UWB receiver, a low-power mixer for IEEE 802.11a receiver and a low-power mixer for WCDMA receiver. The designed chips are fabricated in TSMC 0.18-μm CMOS process. At first, we propose a UWB low noise amplifier (LNA) for low-voltage and low power application. This LNA is designed based on a current-reused topology that leads to a simplified RLC circuit for broadband input matching. LC matching method is introduced at output port for reducing power consumption. The measured results of the designed LNA achieved an average power gain (S21) of 9 dB from 3 to 5.6 GHz, an input reflection coefficient (S11) of less than –9 dB from 2 to 11 GHz, and an output reflection coefficient (S22) of less than –8 dB from 3 to 7.5 GHz. The measured noise figure is 4.6 to 5.3 dB from 3 to 5.6 GHz. The measured input third-order-intercept point (IIP3) is 2 dBm at 5.3 GHz. The dc power consumption is 9 mW with 1-V supply voltage. Secondly, we designed a low voltage and high linear mixer for WLAN IEEE 802.11a receiver. The presented mixer leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measured results of the designed mixer achieve: 7.6 dB power conversion gain, 11.4dB double side band (DSB) noise figure, 3 dBm input third-order intercept point (IIP3), and total 2.45 mW dc power consumption including output buffers from 1V supply voltage. The output buffer consumed about 2 mW. The achieved LO-RF, LO-IF and RF-IF isolation are up to 37.8 dB, 54.8 dB and 38.2 dB, respectively. Finally, we propose a mixer for low voltage and high isolated WCDMA receiver. The measured results of the proposed mixer achieve: 7 dB power conversion gain, 10.4 dB double side band (DSB) noise figure, -2 dBm input third-order intercept point (IIP3), and the total 2.2 mW dc power consumption including output buffers from 1V supply voltage. The output buffer consumed about 1.96 mW. Excellent LO-RF, LO-IF, and RF-IF isolation up to 49 dB, 39.5 dB and 57.3 dB, respectively, are achieved. Zhi-Ming Lin Jeen-Sheen Row 林志明 羅鈞壎 2007 學位論文 ; thesis 99 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 博士 === 國立彰化師範大學 === 電機工程學系 === 96 === In the recent years, the low-power, low-cost, and high integration have become the trend for communication ICs. In this thesis, we proposed a low-power low noise amplifier (LNA) for UWB receiver, a low-power mixer for IEEE 802.11a receiver and a low-power mixer for WCDMA receiver. The designed chips are fabricated in TSMC 0.18-μm CMOS process. At first, we propose a UWB low noise amplifier (LNA) for low-voltage and low power application. This LNA is designed based on a current-reused topology that leads to a simplified RLC circuit for broadband input matching. LC matching method is introduced at output port for reducing power consumption. The measured results of the designed LNA achieved an average power gain (S21) of 9 dB from 3 to 5.6 GHz, an input reflection coefficient (S11) of less than –9 dB from 2 to 11 GHz, and an output reflection coefficient (S22) of less than –8 dB from 3 to 7.5 GHz. The measured noise figure is 4.6 to 5.3 dB from 3 to 5.6 GHz. The measured input third-order-intercept point (IIP3) is 2 dBm at 5.3 GHz. The dc power consumption is 9 mW with 1-V supply voltage. Secondly, we designed a low voltage and high linear mixer for WLAN IEEE 802.11a receiver. The presented mixer leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measured results of the designed mixer achieve: 7.6 dB power conversion gain, 11.4dB double side band (DSB) noise figure, 3 dBm input third-order intercept point (IIP3), and total 2.45 mW dc power consumption including output buffers from 1V supply voltage. The output buffer consumed about 2 mW. The achieved LO-RF, LO-IF and RF-IF isolation are up to 37.8 dB, 54.8 dB and 38.2 dB, respectively. Finally, we propose a mixer for low voltage and high isolated WCDMA receiver. The measured results of the proposed mixer achieve: 7 dB power conversion gain, 10.4 dB double side band (DSB) noise figure, -2 dBm input third-order intercept point (IIP3), and the total 2.2 mW dc power consumption including output buffers from 1V supply voltage. The output buffer consumed about 1.96 mW. Excellent LO-RF, LO-IF, and RF-IF isolation up to 49 dB, 39.5 dB and 57.3 dB, respectively, are achieved.
author2 Zhi-Ming Lin
author_facet Zhi-Ming Lin
Jun-da chen
陳俊達
author Jun-da chen
陳俊達
spellingShingle Jun-da chen
陳俊達
Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
author_sort Jun-da chen
title Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
title_short Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
title_full Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
title_fullStr Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
title_full_unstemmed Design and Implementation of CMOS Radio-Frequency Chip for Low Power Radio Communication
title_sort design and implementation of cmos radio-frequency chip for low power radio communication
publishDate 2007
url http://ndltd.ncl.edu.tw/handle/25221535897800912744
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