Software Design of Communication Performance Estimation for System Synthesis
碩士 === 國立中山大學 === 電機工程學系研究所 === 96 === In a multiprocessor system-on-chip (MPSOC), parallel processors are utilized to enhance overall performance. However, the communication between processors and memory modules can affect overall performance significantly. We proposed a software design of commun...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95gdpu |
| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 96 === In a multiprocessor system-on-chip (MPSOC), parallel processors are utilized to enhance overall performance. However, the communication between processors and memory modules can affect overall performance significantly. We proposed a software design of communication performance estimation for system synthesis. We designed a hardware simulator of mesh communication architecture of MPSOC. We implemented the simulator of router nodes in SystemC language. An analytical communication performance estimation model can be trained with data measured from communication simulation. It can then be utilized for estimating inter-processor communication performance in an MPSOC.
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