An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications
碩士 === 國立清華大學 === 電機工程學系 === 96 === Recently, orthogonal frequency division multiple access (OFDMA) systems have been regarded as next generation communication technique. OFDMA systems suffer the same problems as orthogonal frequency division multiplexin (OFDM) communication, especially in frequency...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/70304011325218914042 |
id |
ndltd-TW-096NTHU5442105 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-096NTHU54421052015-11-27T04:04:17Z http://ndltd.ncl.edu.tw/handle/70304011325218914042 An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications 適用於多重輸入輸出都會型寬頻無線網路通訊系統之基頻處理器矽智財設計 Hsin-Yi Yu 尤欣怡 碩士 國立清華大學 電機工程學系 96 Recently, orthogonal frequency division multiple access (OFDMA) systems have been regarded as next generation communication technique. OFDMA systems suffer the same problems as orthogonal frequency division multiplexin (OFDM) communication, especially in frequency synchronization and channel impairment. An uplink OFDMA receiver faces problems of multiple frequency offsets and multipath channels in an OFDM symbol because of multiuser transmission. Therefore, a base station (BS) design becomes a more challenging task. Especially when multi-input multi-output (MIMO) technology is applied to OFDMA communication to improve detection quality or to increase data rate, synchronization and channel estimation problems become more complicated. In this thesis, a prototype of OFDMA uplink transceiver design based on IEEE 802.16e standard is proposed and implemented. The proposed transceiver consists of an inter-carrier interference/ multiple-access interference (ICI/MAI) canceller, an ICI-cancellation-based carrier frequency offset (CFO) estimator, a channel estimator, a MIMO detector and a general OFDMA baseband engine. The proposed architecture is aim to estimate the CFO with low cost but high precision based on ICI cancelation and with the help of channel estimation by binary search method. Linear interpolation/extrapolation and coefficient approximation technique are applied in channel estimation for reducing hardware complexity but still with high performance. The proposed architecture has 342 gate-count saving compared to conventional one and is implemented in field-programmable gate array (FPGA) board and integrated in SoC platform. Hsi-Pin Ma 馬席彬 2008 學位論文 ; thesis 63 en_US |
collection |
NDLTD |
language |
en_US |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 國立清華大學 === 電機工程學系 === 96 === Recently, orthogonal frequency division multiple access (OFDMA) systems have been regarded as next generation communication technique. OFDMA systems suffer the same problems as orthogonal frequency division multiplexin (OFDM) communication, especially in frequency synchronization and channel impairment. An uplink OFDMA receiver faces problems of multiple frequency offsets and multipath channels in an OFDM symbol because of multiuser transmission. Therefore, a base station (BS) design becomes a more challenging task. Especially when multi-input multi-output (MIMO) technology is applied to OFDMA communication to improve detection quality or to increase data rate, synchronization and channel estimation problems become more complicated.
In this thesis, a prototype of OFDMA uplink transceiver design based on IEEE 802.16e standard is proposed and implemented. The proposed transceiver consists of an inter-carrier interference/ multiple-access interference (ICI/MAI) canceller, an ICI-cancellation-based carrier frequency offset (CFO) estimator, a channel estimator, a MIMO detector and a general OFDMA baseband engine. The proposed architecture is aim to estimate the CFO with low cost but high precision based on ICI cancelation and with the help of channel estimation by binary search method. Linear interpolation/extrapolation and coefficient approximation technique are applied in channel estimation for reducing hardware complexity but still with high performance. The proposed architecture has 342 gate-count saving compared to conventional one and is implemented in field-programmable gate array (FPGA) board and integrated in
SoC platform.
|
author2 |
Hsi-Pin Ma |
author_facet |
Hsi-Pin Ma Hsin-Yi Yu 尤欣怡 |
author |
Hsin-Yi Yu 尤欣怡 |
spellingShingle |
Hsin-Yi Yu 尤欣怡 An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
author_sort |
Hsin-Yi Yu |
title |
An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
title_short |
An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
title_full |
An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
title_fullStr |
An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
title_full_unstemmed |
An Uplink Baseband Processor IP for Mobile MIMO WiMAX Communications |
title_sort |
uplink baseband processor ip for mobile mimo wimax communications |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/70304011325218914042 |
work_keys_str_mv |
AT hsinyiyu anuplinkbasebandprocessoripformobilemimowimaxcommunications AT yóuxīnyí anuplinkbasebandprocessoripformobilemimowimaxcommunications AT hsinyiyu shìyòngyúduōzhòngshūrùshūchūdōuhuìxíngkuānpínwúxiànwǎnglùtōngxùnxìtǒngzhījīpínchùlǐqìxìzhìcáishèjì AT yóuxīnyí shìyòngyúduōzhòngshūrùshūchūdōuhuìxíngkuānpínwúxiànwǎnglùtōngxùnxìtǒngzhījīpínchùlǐqìxìzhìcáishèjì AT hsinyiyu uplinkbasebandprocessoripformobilemimowimaxcommunications AT yóuxīnyí uplinkbasebandprocessoripformobilemimowimaxcommunications |
_version_ |
1718137892273913856 |