| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 96 === In modern digital integrated circuit, high performance design with low power dissi-
pation has been accomplished nowadays as the feature size of transistor keeps scaling
down. However, adopting low power techniques to the digital circuit design is crucial
and difficult in engineering practice at current stage. Cell-based flow is the most pop-
ular design flow in the various customized IC design market. Based on these fact, we
proposed a simple cell optimization flow to develop a cell library which enable a low volt-
age operation under 1.0V. Meanwhile, voltage scaling and multi-VCC partitioning low
power technique are also adopted to the modified cell-based design flow. For the isola-
tion between different power domain, the library based macro design is implemented for
the test circuit. By separating power nets into individual voltage block, two independent
regions are provided by each corresponding supply voltages.
According to the simulation results, by using the low voltage library and power
reduction methods merged to the designed flow, a power reduction compared with the
original test circuit approaching 70% can be achieved. Moreover, the test design can
provides two self-defined voltage blocks and voltage scaling options (VCC=1.0V-0.8V;
VCCL=1.0V-0.6V) without any performance degradation.
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