SoPC-based C-Means Clustering Algorithm Design

碩士 === 國立臺灣師範大學 === 資訊工程研究所 === 96 === A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider...

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Bibliographic Details
Main Authors:	Chih Chieh Hsu, 許智傑
Other Authors:	Wen-Jyi Hwang
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/43599076019067384097

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spelling	ndltd-TW-096NTNU53920092015-10-13T13:08:49Z http://ndltd.ncl.edu.tw/handle/43599076019067384097 SoPC-based C-Means Clustering Algorithm Design 在可程式化系統晶片上之C-Means分群演算法設計 Chih Chieh Hsu 許智傑碩士國立臺灣師範大學資訊工程研究所 96 A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on table lookup, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement.Numerical results reveal that our design is an effective solution with low hardware complexity and high computation performance for c-means design. Wen-Jyi Hwang 黃文吉 2008 學位論文 ; thesis 43 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣師範大學 === 資訊工程研究所 === 96 === A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on table lookup, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement.Numerical results reveal that our design is an effective solution with low hardware complexity and high computation performance for c-means design.
author2	Wen-Jyi Hwang
author_facet	Wen-Jyi Hwang Chih Chieh Hsu 許智傑
author	Chih Chieh Hsu 許智傑
spellingShingle	Chih Chieh Hsu 許智傑 SoPC-based C-Means Clustering Algorithm Design
author_sort	Chih Chieh Hsu
title	SoPC-based C-Means Clustering Algorithm Design
title_short	SoPC-based C-Means Clustering Algorithm Design
title_full	SoPC-based C-Means Clustering Algorithm Design
title_fullStr	SoPC-based C-Means Clustering Algorithm Design
title_full_unstemmed	SoPC-based C-Means Clustering Algorithm Design
title_sort	sopc-based c-means clustering algorithm design
publishDate	2008
url	http://ndltd.ncl.edu.tw/handle/43599076019067384097
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SoPC-based C-Means Clustering Algorithm Design

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