The back-end of layout vs. schematic checker for microwave multi-layer circuits:schematic mapping
碩士 === 臺灣大學 === 電子工程學研究所 === 96 === This thesis is focus on the back-end of layout vs. schematic check. It is divided into three parts. The first part is to convert shematic dsn file into a graphic representation. The second part is to check the DC path between any circuit ports. The third part is t...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/76614278152137678573 |