VLSI Architecture Design of Prediction Core and Cache in Super High Definition H.264/AVC Encoder
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === With the progress of video technology, the image resolution is getting finer, and this directly contributes to the video quality. From VCD to high definition (HD) contents, the video quality stays on a fast growing track. In the foreseeable future, camcorders an...
Main Authors: | Wei-Yin Chen, 陳威尹 |
---|---|
Other Authors: | Liang-Gee Chen |
Format: | Others |
Language: | en_US |
Online Access: | http://ndltd.ncl.edu.tw/handle/fb7kwe |
Similar Items
-
Parallel VLSI Architectures for High-Definition H.264/AVC Motion Estimation
by: Kao, Chao-Yang, et al.
Published: (2009) -
Adaptive Multi-Frame Algorithms and VLSI Architecture for Fast H.264/AVC Encoding
by: Tsung-Han Yang, et al.
Published: (2008) -
VLSI Architecture for Deblocking Filter in H.264/AVC
by: Jian-Ping Zeng, et al.
Published: (2007) -
VLSI Architecture for Deblocking Filter in H.264/AVC
by: Chung-Ming Chen, et al.
Published: (2007) -
A VLSI Architecture For H.264/AVC Motion Estimation
by: Hung-YuChang, et al.
Published: (2012)