Design and Analysis of High-Speed On-Chip Transceiver
碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === In this thesis, the design of a high speed serial link transceiver is presented. The major factors limiting the performance of high-speed transceivers are the bandwidth of the channel. We use a combination of a 4-level pulse amplitude modulation (4-PAM) to reduc...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47296576761729071003 |