Design and Analysis of High-Speed On-Chip Transceiver
碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === In this thesis, the design of a high speed serial link transceiver is presented. The major factors limiting the performance of high-speed transceivers are the bandwidth of the channel. We use a combination of a 4-level pulse amplitude modulation (4-PAM) to reduc...
Main Authors: | Shih-Ming Tsai, 蔡適名 |
---|---|
Other Authors: | 賴飛羆 |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/47296576761729071003 |
Similar Items
-
A high speed ATM-based user-network interface transceiver chip design
by: Lu, Qin Yong, et al.
Published: (1995) -
The Design and Implementation of High-Speed Wireline Transceivers in CMOS Technology
by: Ming-Shuan Chen, et al.
Published: (2008) -
High-Speed Bidirectional Transceiver
by: Ruei-Iun Pu, et al.
Published: (2008) -
High speed、LVDS transceiver
by: 蕭聖文
Published: (2004) -
BIST Design for Jitter Injection of High Speed Transceivers
by: Kong-Ping Li, et al.
Published: (2005)