Formal-Assisted Buffer Insertion
碩士 === 國立臺灣大學 === 電機工程學研究所 === 96 === Along with the progress of VLSI technology, buffer insertion plays an increasingly important role in improving circuit performance. Prior works (e.g. VGDP algorithm) are focused on enhancing the running time of buffer insertion algorithms, while our main objecti...
Main Authors: | Kai-Chu Wu, 吳鎧竹 |
---|---|
Other Authors: | 黃鐘揚 |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/20044781400629371615 |
Similar Items
-
A Formal-Assisted Buffer Insertion and Gate Sizing Technique Considering Multi-Corner Multi-Mode Timing Constraints
by: Man-Yu Li, et al.
Published: (2011) -
On Power-State-Aware Routing and Buffer Insertion
by: Ming-Hua Wu, et al.
Published: (2007) -
Clock Tree Synthesis with Buffer Insertion/Sizing
by: Chu, Hao-Hsien, et al.
Published: (2013) -
Buffer Insertion for ASIC and FPGA Designs
by: Yi-Ru He, et al.
Published: (2007) -
High Level Synthesis with Buffer Insertion
by: Feng Ming Chang, et al.
Published: (2006)