A 1.8V 0.35um 90dB SNDR Sigma-Delta Modulator Chip Design for Audio Application

• Main Authors: Chi-Wen Liu, 劉繼文
• Other Authors: Jhin-Fang Huang
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/88572364795968891106

碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === In recent years, with rapid growth of the marketing in the consumer electronics products, small and lightweight, high-quality and long operating time of audio, communications, video products have begun to attract. Multimedia products, such as: MP3 player has been a mainstream product of the consumer electronics market. In modern VLSI design, Sigma-Delta modulator for audio application can achieve high resolution in conversion analog into digital signal further to obtain high-quality. As for increase the operating time, in addition to increased battery capacity, another way is to reduce the power consumption of circuit. The most effective way to reduce the power consumption in a mixed-signal integrated circuit is to reduce its supply voltage; the other way is using more advanced CMOS process. But implement with high-technique CMOS process, the cost is unacceptable for market. Therefore, low-voltage design is the best choice. However, design a high resolution analog circuit in low-voltage environment is complicated. It is a great challenge to maintain the desired performance of the A/D converter while the supply voltage is reduced. In this thesis, a high resolution fourth-order fourth-bit Sigma-Delta modulator for audio application is presented. The main error mechanisms caused by different non-idealities of the analog building blocks are reviewed and discussed, and behavioral models and the degradation of the performance of Sigma-Delta modulators will be presented. The modulator is fabricated in TSMC standard 0.35μm CMOS 2P4M process. The maximum SNDR of the modulators is 90dB within a bandwidth of 20KHz and the sampling frequency of the modulator is 2.56MHz with a 1.8V power supply.