| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 96 === The phase lock loop in integrated was a quite widely application in communication, and the product is miniaturization, powerful function, accumulates the body and high frequency has become the inevitable tendency for fast growth wireless communication industry. The purpose of this thesis introduces the analysis frequency synthesizer and the actual design process of the frequency synthesizer. Due to the conventional integer-N frequency synthesizers suffer from fundamental tradeoffs among frequency step size, loop bandwidth, phase noise, and reference spurs. It focus on improve circuit performance, and design a better circuit in process limit.
In this thesis, we propose two phase-locked loops in TSMC 0.35um CMOS 2P4M process technology. The first phase-locked loop is a frequency synthesizer for Trunked Radio System Applications PLL. This proposed synthesizer covers a wide frequency range from 320MHz to 1100MHz. The second phase-locked loop is also made in 0.35um process, and the frequency is from 2.1GHz to 3.1GHz for ISM band. Because of phase noise is very important to communication system, especially in offering a steady frequency of going up and down. If the phase noise does not meet to the specification, it is easy to grade of frequency reached to receive interfere by the phase noise. The ring-oscillator is designed in lower phase noise comparing with conventional ring-oscillator. On the other hand, the two circuits design reduces chip area efficiently as a result of non-inductive.
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