Dynamic Dispatching Rule Considering Bottleneck Resources in Semiconductor Assembly Factory

• Main Authors: Jin-Lin Huo, 霍錦霖
• Other Authors: 張玉鈍
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/7a2mt5

碩士 === 國立臺北科技大學 === 工業工程與管理研究所 === 96 === The research is based on a case of semiconductor assembly factory in North Taiwan. The current dispatching rule of the factory is based on accumulate cycle times only. We know that setups are needed when different package type is processed successively at bonding and molding stations. Since the setup time could last few minutes to hours, the WIP in front of bonding and molding stations fluctuates so much that two stages of processes become bottlenecks in irregular pattern. That means bottleneck shifting. The research is devoted to build the factory simulation model and develop dynamic dispatching rule considering bottleneck resources. The purpose is to decrease the situation of bottleneck shifting, reduce average cycle time, and increase throughput. In order to find the suitable were conducted parameter setting for the dynamic dispatching rule, in assembly area, different experiments. The result shows that dynamic dispatching rule can decrease average CT significantly, especially at molding station where the improvement is about 25%, and also increase average TH. When the parameters were set to BL2 as 0.75 days, BM1 as 4 hours, BM2 as 8 hours, and ML2 as 6.3 days, CT is reduced significantly. When the parameters were set to BL2 as 1.25 days, BM1 as 8 hours, BM2 as 8 hours, and ML2 as 2.7 days, TH is increased significantly. When the parameters were set to BL2 as between 0.75 and 1.25 days, BM1 as between 4 and 8 hours, BM2 as 8 hours, and ML2 as 4.5 days, CT and TH are both improved at assembly factory.