| Summary: | 碩士 === 國立臺北科技大學 === 電機工程系研究所 === 96 === This paper aims at simulating the operating behavior of a fully-digitalized synchronously-rectified (SR) forward converter, via co-simulating the Active-HDL software with the MATLAB/Simulink software. Most of all, the information on the output voltage is sampled without any analog-to-digital converter (ADC), based on the one-comparator counter-based sampling strategy which is implemented mainly by the field programmable gate array (FPGA) and the VHSIC hardware description language (VHDL). Besides, the triangular wave injection is presented herein to improve the sampling accuracy, so as to make the output voltage as close as possible to the prescribed setting. In this thesis, first of all, the associated theoretical derivation is introduced, and secondly some simulated and experimental results are provided.
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