Design of Low-Voltage Wideband Delta Sigma Modulators

碩士 === 淡江大學 === 電機工程學系碩士班 === 96 === With the improvement of the process of the integrated circuit, nanometer technology is applied. However it is not benefited greatly to design and implement the analog circuit due to the threshold voltage is less decreased. Due to the improvement of the process, t...

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Bibliographic Details
Main Authors: Shuo-Chau Chen, 陳碩超
Other Authors: Chien-Hung Kuo
Format: Others
Language:en_US
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/32533411417767178987
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Summary:碩士 === 淡江大學 === 電機工程學系碩士班 === 96 === With the improvement of the process of the integrated circuit, nanometer technology is applied. However it is not benefited greatly to design and implement the analog circuit due to the threshold voltage is less decreased. Due to the improvement of the process, the power supply has to decrease in proportion to the breakdown voltage of the gate. The requirement of the low voltage circuit design is getting bigger and bigger. The low voltage circuit design can effectively reduce the volume and weight of the battery. It satisfies the portability and the battery life of the portable wireless communications products. The improvement of the process and architecture, the wideband applications grow up greatly. ADSL is one of the most popular methods of the internet connection. The number of the ADSL users is increasing quickly. In order to improve the development of ADSL, low cost and high performance IC is required. In mention of the cost, the key point to implement an efficient AFE is how to integrate each element effectively. It is the concept of SOC. Digital IC get advance due to the process improvement, but analog IC do not. In this thesis, we discuss and design the ADC work in low supply voltage to integrate with the digital integrated circuit more compactly. We present a low voltage wideband delta-sigma modulator. The MASH architecture is combined with two structures. The first stage is low distortion structure and the second stage is traditional feedback one. Each stage performs second-order noise shaping, and the entire system can accomplish fourth-order noise shaping. Double sampling is used to promote the clock efficiency and relax the requirement of the opamps. The proposed modulator has been implemented in a 0.13