Design and Implementation of Scalable Arbiters for SoC On-Chip Network
碩士 === 大同大學 === 資訊工程學系(所) === 96 === System-on-chip (SoC) design is very popular in electronic industry. There are many advantages by using SoC design, such as cost down, area reduction, and low power consumption. But it also brings a lot of challenges like system complexity. Hence, many systems are...
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| Format: | Others |
| Language: | en_US |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68579081218809552122 |
| Summary: | 碩士 === 大同大學 === 資訊工程學系(所) === 96 === System-on-chip (SoC) design is very popular in electronic industry. There are many advantages by using SoC design, such as cost down, area reduction, and low power consumption. But it also brings a lot of challenges like system complexity. Hence, many systems are integrated with existing IP cores by using on-chip communication architecture.
An arbiter plays an important role in the on-chip communication architecture. The purpose of this thesis is to design scalable arbiters and the users can define their arbitration algorithms. With high integrations, having a scalable arbiter is indispensably.
Besides, we also proposed two more designs to improve the hardware costs and the speed for the priority based arbiter architecture. The designs are written in VHDL language and verified in Quartus. The experiment results which were compared to Round-Robin (RR) algorithm show that the logic element of the architecture IV is 0.89 times the RR algorithm. All the total clock time of the four architectures are shorter than the RR algorithm and the shortest one is 0.43 times the RR algorithm.
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