| Summary: | 碩士 === 雲林科技大學 === 電機工程系碩士班 === 96 === This thesis is focused on the investigation of hardware design of channel decoders in DVB-T systems. The modular designs presented in this thesis include Reed-Solomon (RS) and convolutional coders, RS and Viterbi decoders, and the inner and outer interleaver/de-interleavers. The RS decoder uses the inverse-free Berlekamp-Massey algorithm and then searches error locations through parallel-processing units. Under our design, the searching time for the decoder has been reduced to about one fourth of that required by the original algorithm. All of the building blocks for the decoder have been separately tested and verified. The overall decoding system synthesized with Verilog Hardware Description Language (HDL). By using developing tools, namely, Altera Quartus II 7.1 and ModelSim simulating software, we have demonstrated the function of the hardware design.
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