A Low-Cost Register Extension Approach For RISC Processors

• Main Authors: Hong-Sheng Lin, 林洪聖
• Other Authors: Rong-Guey Chang
• Format: Others
• Language: en_US
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/48272694169108844916

碩士 === 國立中正大學 === 資訊工程所 === 97 === Traditionally, the number of architected registers is typically much smaller than the number of physical registers. To improve performance, embedded processors or general purpose processors have been equipped with a big physical register file recently. However, this trend is always limited by the constraints of instruction set architecture (ISA). Thus, the way to release these constraints to extend the register file has become an important issue. One of major constraints arises from the encoding space of register fields in an instruction. The width of a register field determines the number of architected register, which limits the extension range of architected registers and thus also directly expands code size. In addition, if a register field becomes wider, wider instructions also complicate decoding process in the pipeline, stretching clock cycles, increasing power consumption. Moreover, especially for low-end processors, encoding space are extremely limited due to area and power considerations. Modern processors such as MIPS ARM Alpha UltraSPARC POWER etc. their numbers of exposed architected registers just range from 16 to 32 at ISA level. In other words, the width of register field around 4 to 5 bits, which restricts the usage of physical register at the cost of performance penalty. Therefore, we propose an approach to solve the above ISA constraints.