A Bounded Minimal Skew Grid Router for 3 Dimensional Integrated Circuits
碩士 === 中原大學 === 資訊工程研究所 === 97 === 3D IC integration of circuits is a promising approach to integrate a large system on a single chip. The average global wire length is reduced drastically. In this paper, we present a bounded minimal skew grid router for Three Dimensional Integrated Circuits. We rou...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00933647138567489448 |
| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 97 === 3D IC integration of circuits is a promising approach to integrate a
large system on a single chip. The average global wire length is reduced
drastically. In this paper, we present a bounded minimal skew grid router
for Three Dimensional Integrated Circuits. We route a net layer by layer
starting from the top layer. All terminals on the layer are routed to form a
minimum skew subtree. The root of the subtree is projected to the layer
below. This projected point will be connected with the root of the subtree
of the projected layer. The connection between layers is implemented by
a TSV. This routing procedure is repeated for all layers. Finally, a
minimum skew routing tree is completed. The skew of the routing is
bounded by the height of the tree. Experimental results show that our
algorithm can generate routing with very small skew. In average, the
skew is 0.73% of the maximum latency in all 25 test cases. The skew is
smaller than 9 units in all cases. Experimental results have shown that our
algorithm is effective in skew minimization.
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