A Self-align Enhancement mode FET for DCFL in Monolithic Microwave Integration Circuit Application

• Main Authors: Chi-Wen Liao, 廖繼文
• Other Authors: Shih-Wei Tan
• Format: Others
• Language: zh-TW
• Published: 2009
• Online Access: http://ndltd.ncl.edu.tw/handle/43654308773700674145

碩士 === 清雲科技大學 === 電機工程研究所 === 97 === Because the wireless communication and the optical fiber communication's development rapidly, the bandwidth insufficiency has been the existence question, therefore the part walks toward the high-frequency response's direction is the consistent tendency. In recent year, doped-channel heterostructure field-effect transistors (DCFETs) with a high current density and superior microwave power performance was developed and characterized and Schottky gate performance and thermal stability, it has been widely investigated for microwave power devices and high-speed devices. In the paper, we success fabrication DD model of both p-n heterojunction and were investigated at different ambient temperatures. The DD model together with a numerical method that could be used to extract the parameters has described well the characteristics of the proposed p-n junction under forward bias. According to fore-mentioned, we demonstrate simple that a doped-channel field-effect transistor HDCFET structure, using an additional p+-GaAs cap layer and self-aligned, simultaneously obtains both p-n junction and Schottky junction to fabricate the enhancement mode and depletion mode of HDCFET (EHDCFET and DHDCFET) on the same chip, thus implementing direct-coupled field effect transistor logic (DCFL) circuit.