| Summary: | 碩士 === 逢甲大學 === 電子工程所 === 97 === Polycrystalline silicon thin-film transistors(Poly-Si) are widely used in various field, including active-matrix liquid crystal displays(AM-LCDs), solar cells and three-dimensional(3-D) integrated circuit because of their high carrier mobility and driving current. It is expected that these devices can be fabricated on insulating substrate for the manufacturing and applications of large-area microelectrons. It is widely known that the high electric field induced near the drain causes several undesirable effects in the device electrical characteristics, including the large leakage current, kink effect, and hot carrier effect. In this thesis, a high-performance bottom-gated polycrystalline thin-film transistor with drain extend field plate is proposed and demonstrated. The field plate can spread the drain electric field out and change the electron current path to reduce the impact ionization near the drain area. We also use ISE-TCAD to simulate the electric field, electron current density, and impact ionization distributions of the proposed TFT structure to investigate the device performances. Our experimental results show that the on-current of the proposed TFT is higher than that of the conventional structure, and the kink effect and leakage current are improved simultaneously. In addition, the device stability, such as threshold voltage shift and transconductance degradation under a high gate bias is also improved by the design of drain extended field plate. The current and electric field splited structure of the proposed TFT is also beneficial to scaling down the device for a better performance.
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