Design of on-chip Balun with high coupling factor in CMOS Technology
碩士 === 國立中興大學 === 電機工程學系所 === 97 === This thesis uses coupled-line theory [2] , [3] to extract the odd and even mode capacitances of device, and to analyze the characteristics of on-chip Balun. The thesis mainly includes four experiment topics. The first topic addresses planar Marchand Balun. Adopti...
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ndltd-TW-097NCHU54410102016-04-29T04:19:42Z http://ndltd.ncl.edu.tw/handle/78501427421943472181 Design of on-chip Balun with high coupling factor in CMOS Technology CMOS高耦合分波器之設計 Szu-Yuan Chen 陳思源 碩士 國立中興大學 電機工程學系所 97 This thesis uses coupled-line theory [2] , [3] to extract the odd and even mode capacitances of device, and to analyze the characteristics of on-chip Balun. The thesis mainly includes four experiment topics. The first topic addresses planar Marchand Balun. Adopting the approach of capacitance extraction to compare differences characteristics, the results show that the layout of overlap structure has better bandwidth and amplitude imbalance than planar structure,Adopting EM simulation, the bandwidth improves 2.5 times compared with the planar structure, moreover amplitude imbalance improves approximately 9% . The second topic describes the Balun design with various metal widths in metal coil. Using the design of various metal width to reduce metal resistance, keeping identical conditions of self-inductance,the results increase the Q values, and decrease the insertion loss. The DC resistance improvements approximately 12.5% . The third topic addresses the stacked Balun. The different layout is designed to compare device characteristics in the experiment, the equivalent capacitors of even and odd modes are calculated using device corss-section.In order to analyze the performances of amplitude imbalance, we obtain that the stacked structure causes high coupling factor. Therefore, measurement results shows that the amplitude imbalance achieves to 0.2 dB and the phase imbalance achieve to 0°~8°. The last topic describes stacked symmetry Balun design. Design different return layers to characterize device performances in experiment. The small even-mode capacitance is resulted from the series connection, and large odd-mode capacitance is due to the shunt connection of metal layers in proposed device. Therefore, the coupling factor of these devices approximated to the value of 0.984. Therefore, measurement result shows that the average amplitude imbalance achieves to 0.163 dB. 許�睇� 學位論文 ; thesis 87 zh-TW |
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碩士 === 國立中興大學 === 電機工程學系所 === 97 === This thesis uses coupled-line theory [2] , [3] to extract the odd and even mode capacitances of device, and to analyze the characteristics of on-chip Balun. The thesis mainly includes four experiment topics. The first topic addresses planar Marchand Balun. Adopting the approach of capacitance extraction to compare differences characteristics, the results show that the layout of overlap structure has better bandwidth and amplitude imbalance than planar structure,Adopting EM simulation, the bandwidth improves 2.5 times compared with the planar structure, moreover amplitude imbalance improves approximately 9% .
The second topic describes the Balun design with various metal widths in metal coil. Using the design of various metal width to reduce metal resistance, keeping identical conditions of self-inductance,the results increase the Q values, and decrease the insertion loss. The DC resistance improvements approximately 12.5% .
The third topic addresses the stacked Balun. The different layout is designed to compare device characteristics in the experiment, the equivalent capacitors of even and odd modes are calculated using device corss-section.In order to analyze the performances of amplitude imbalance, we obtain that the stacked structure causes high coupling factor. Therefore, measurement results shows that the amplitude imbalance achieves to 0.2 dB and the phase imbalance achieve to 0°~8°.
The last topic describes stacked symmetry Balun design. Design different return layers to characterize device performances in experiment. The small even-mode capacitance is resulted from the series connection, and large odd-mode capacitance is due to the shunt connection of metal layers in proposed device. Therefore, the coupling factor of these devices approximated to the value of 0.984. Therefore, measurement result shows that the average amplitude imbalance achieves to 0.163 dB.
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許�睇� |
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許�睇� Szu-Yuan Chen 陳思源 |
author |
Szu-Yuan Chen 陳思源 |
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Szu-Yuan Chen 陳思源 Design of on-chip Balun with high coupling factor in CMOS Technology |
author_sort |
Szu-Yuan Chen |
title |
Design of on-chip Balun with high coupling factor in CMOS Technology |
title_short |
Design of on-chip Balun with high coupling factor in CMOS Technology |
title_full |
Design of on-chip Balun with high coupling factor in CMOS Technology |
title_fullStr |
Design of on-chip Balun with high coupling factor in CMOS Technology |
title_full_unstemmed |
Design of on-chip Balun with high coupling factor in CMOS Technology |
title_sort |
design of on-chip balun with high coupling factor in cmos technology |
url |
http://ndltd.ncl.edu.tw/handle/78501427421943472181 |
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