| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 97 === In the 3GPP-LTE (Third Generation Partnership Project - Long Term Evolution), channel coding technique is framed to employ the turbo code, which is skilled in error correction. With the development of the mobile communication systems, the uplink and downlink speeds are 50Mbps and 100Mbps, respectively. It makes the multimedia functions in the wireless communication devices more flexible.
The 3GPP-LTE turbo code, dividing into 188 levels, has the block sizes between 40 and 6144 bits. The interleaver address for every block is immediately computed by the interleaver address generator. Hardware implementation of the interleaver algorithm with quadratic polynomial permutation may lead to a waste of chip area and power consumption. Therefore, this thesis aims to calculate the interleaver address by the recursive computation. Only adders and multiplexers are needed during the recursive computation so that the effectiveness of hardware implementation is increased. However, when x 2K, the recursive computation containing (x mod K) will carry out the subtraction more than twice, which will affect the hardware performance of the interleaver. In this thesis, the recursive computation would be modified slightly so as to output one interleaver address for each clock cycle and achieve high throughput.
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