| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core area is 0.4536 mm2.
Moreover, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters. This scheme includes the current subtraction circuit to increase the sampling current accuracy and the selected-code method to reduce the testing time. As a result, the proposed method can greatly shorten the test time and relax the demands on high precision test equipments, and consequently reduce test cost significantly.
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