The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results...
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ndltd-TW-097NCKU54420052015-11-23T04:03:12Z http://ndltd.ncl.edu.tw/handle/76371604221474286432 The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters 電流導向式數位類比轉換器之設計及其線性度內建自我測試 Su-Ling Huang 黃素鈴 碩士 國立成功大學 電機工程學系碩博士班 97 This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core area is 0.4536 mm2. Moreover, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters. This scheme includes the current subtraction circuit to increase the sampling current accuracy and the selected-code method to reduce the testing time. As a result, the proposed method can greatly shorten the test time and relax the demands on high precision test equipments, and consequently reduce test cost significantly. Soon-Jyh Chang 張順志 2008 學位論文 ; thesis 87 en_US |
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碩士 === 國立成功大學 === 電機工程學系碩博士班 === 97 === This thesis presents the design concept, circuit analysis, and practical considerations of implementation for a 10-bit 500-MSample/s current steering digital-to-analog converter. It is fabricated in TSMC standard 0.18-�慆 1P6M CMOS process. The measured results show that the differential nonlinearity (DNL) is less than 0.35 LSB (Least Significant Bit), and the integral nonlinearity (INL) is less than 0.6 LSB. The spurious free dynamic range (SFDR) is 60.63 dB with a 25-MHz input signal at a 500-MS/s sampling rate. The power consumption is 28 mW, and the core area is 0.4536 mm2.
Moreover, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters. This scheme includes the current subtraction circuit to increase the sampling current accuracy and the selected-code method to reduce the testing time. As a result, the proposed method can greatly shorten the test time and relax the demands on high precision test equipments, and consequently reduce test cost significantly.
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Soon-Jyh Chang |
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Soon-Jyh Chang Su-Ling Huang 黃素鈴 |
author |
Su-Ling Huang 黃素鈴 |
spellingShingle |
Su-Ling Huang 黃素鈴 The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
author_sort |
Su-Ling Huang |
title |
The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
title_short |
The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
title_full |
The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
title_fullStr |
The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
title_full_unstemmed |
The Design and Linearity Built-In Self-Test of Current-Steering Digital-to-Analog Converters |
title_sort |
design and linearity built-in self-test of current-steering digital-to-analog converters |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/76371604221474286432 |
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